Title:
MEMORY CIRCUIT
Document Type and Number:
Japanese Patent JP2551331
Kind Code:
B2
Abstract:
PURPOSE: To allow recognition of actual synchronization from the outside of αFIFO.
CONSTITUTION: A 8 bit data signal is inputted to 8 bits among 9 bits of FIFOs 1, 2 and a signal for confirming the delay time is inputted to one remaining bit. 8 bits of a 9 bit parallel signal, read out from memory cells 10, 20, are outputted as a data signal and one remaining bit is outputted, as a signal for confirming the delay time, to a comparing circuit 3. The comparing circuits 3 compares the delay time confirmation signals received from the FIFOs 1, 2 and delivers the comparison result to an inhibition circuit 4. The inhibition circuit 4 inhibits provision of read out clock to the read out counter 22 for the FIFO 2 depending on the comparison result thus stopping the frequency dividing operation of the read out counter 22.
Inventors:
NOMURA KENICHI
Application Number:
JP15629893A
Publication Date:
November 06, 1996
Filing Date:
June 02, 1993
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
G11C7/00; (IPC1-7): G11C7/00
Domestic Patent References:
| JPH01119153A | ||||
| JPH0522360A | ||||
| JPH04108241A |
Attorney, Agent or Firm:
Yanagi Kawa Shin
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