Title:
【発明の名称】メモリ搭載パッケージの検査装置
Document Type and Number:
Japanese Patent JP3060580
Kind Code:
B2
Abstract:
PURPOSE:To perform plural tests within one cycle by using a delay circuit to delay the timing, etc., of signals output from plural packages to be tested, and comparing the output signals with desired values using a judgment strobe corresponding to each package to be tested. CONSTITUTION:An address signal 1, an input data signal 2 and a memory control signal 3 generated by a testing device are directly input to a first package 5 to be tested. The signals 1,2 and 3 are input to a delay circuit 8 and delayed by half the cycle and input to a second package 6 to be tested: Therefore, the write and read action of the memory of the package 6 is delayed from that of the memory of the package 5 to be tested by an amount of time equal to that delay. Signals output from the package 6 due to the read action are output with a delay of half the cycle to those output from the package 5 and package selection signals 7 are changed to '0' and '1' at every half the cycle and thereby signals are output alternately from the packages 5,6 as those output from a selection circuit 9.
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Inventors:
Tomomi Goto
Application Number:
JP9254791A
Publication Date:
July 10, 2000
Filing Date:
April 24, 1991
Export Citation:
Assignee:
NEC
International Classes:
G11C29/00; G11C29/56; G01R31/28; (IPC1-7): G01R31/28; G11C29/00
Domestic Patent References:
| JP5673362A | ||||
| JP5357715A | ||||
| JP4305176A | ||||
| JP267977A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)