PURPOSE: To simulate the parallel computer of a scale more than the number of arithmetic elements without changing a program by defining the addresses of the plural virtual arithmetic elements in a main storage device, and simulating the plural virtual arithmetic elements.

CONSTITUTION: An 8M byte space in a main storage device 105 is divided into each 2M byte, and four virtual arithmetic elements are generated. An address converter 102 makes the address spaces of the virtual arithmetic elements correspond to the physical address spaces, an arithmetic processing unit 101 performs an access to any virtual arithmetic element by performing an access to the address. An arithmetic processing unit 101 is turned into a temporary pausing state by an interruption signal transmitted from a controller 103 in each fixed time, and during the temporary pausing state, the controller 103 controls the address converter 102, and selects the next virtual arithmetic element. After the next virtual arithmetic element is selected, the arithmetic processing unit 101 extracts the address of the program saved from the newly selected virtual arithmetic element, and resumes the selected processing.