Title:
【発明の名称】キャッシュ・メモリ内蔵LSI
Document Type and Number:
Japanese Patent JP3082207
Kind Code:
B2
Abstract:
PURPOSE:To curtail the number of terminals of the whole LSI by providing a function for multiplexing an MA and inputting it as a time division to the LSI incorporated with CM. CONSTITUTION:A cache memory 209 of a set associative system utilizes a fact that timings of comparison of a decoding period of a set entry to a monitoring address set part and a tag address to a monitoring address tag part 203 are different from each other. Subsequently, the monitoring address set part and the tag part 203 are inputted as a time division. In such a way, the number of external signal terminals can be curtailed without deteriorating the performance.
Inventors:
Masahiro Kusuda
Application Number:
JP7812190A
Publication Date:
August 28, 2000
Filing Date:
March 27, 1990
Export Citation:
Assignee:
NEC
International Classes:
G06F15/78; G06F12/08; G06F12/12; (IPC1-7): G06F12/08; G06F12/08; G06F15/78
Domestic Patent References:
| JP1181138A | ||||
| JP1321535A | ||||
| JP1217530A | ||||
| JP59157887A | ||||
| JP232439A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)