PURPOSE: To secure the recovery time even in the case that the speed of an operation clock is increased without changing the internal circuit constitution.

CONSTITUTION: An incrementer 4 which can designate permission of operation at the time of transfer of the numerical value of a constant generator 3 to a bus interface device 2 is provided besides an execution device 1, the bus interface device 2 for information transfer, and the constant generator 3. In response to an interrupt INT signal 10, the execution device 1 indicates issue of acknowledge after the end of an instruction executed then. The bus interface device 2 uses a bus cycle start BCYST signal 5, an ST signal 6 indicating the classification of the bus cycle, an FAS signal 7, and a READY signal 8 to execute the interrupt by the indication of acknowledge. When a TIREQ signal 9 generated by a peripheral circuit is made active at this time, the value outputted from the constant generator 3 is incremented in the incrementer 4 by one. Thus, the number of idle cycles Ti to be inserted at the time of interrupt is increased equivalently, and the recovery time is secured.