PURPOSE: To reduce design and production costs for an LSI when delay characteristic of signal path is correctly set as much as possible by taking in design changes in insertion, replacement and deletion of a cell so that a loop consisting of timing decision → design change → arrangement improvement is formed.

CONSTITUTION: Data for a plurality of standard cells are registered in a macro cell library 21, and specified standard cell arrangement and wiring path between standard cells are automatically decided by an automatic arrangement wiring CAD system 23. A delay time calculation device 24 automatically calculates signal path delay time, and a standard for limitation on the signal path delay time is automatically decided by the automatic arrangement wiring CAD system 23. If the standard is not satisfied, changes including process such as insertion, replacement and deletion of delay cell or buffer cell of the signal path are made, and the arrangement of a standard cell other than the delay cell or buffer cell and inter-cell wiring path is automatically corrected as required.