Title:
【発明の名称】再書き込み可能なメモリに対する内部タイミング法およびその回路
Document Type and Number:
Japanese Patent JP3011042
Kind Code:
B2
Abstract:
A circuit (1) generates flexible timing permitting a slow or fast overall timing configuration, and two configurations of the precharge and detecting intervals by providing both with two (short or long) duration levels. For this purpose, the circuit (1) includes a variable, asymmetrical propagation line (5, 37) composed of a succession of elementary delay elements (6-8, 38, 40) enabled or disabled on the basis of memorized logic signals (TIMS, PCS, DETS), the state of which is determined when debugging the memory (100) in which the circuit (1) is implemented.
Inventors:
Luigi Pascatch
Marco Olivo
Cala Maria Gora
Marco Olivo
Cala Maria Gora
Application Number:
JP5038495A
Publication Date:
February 21, 2000
Filing Date:
February 16, 1995
Export Citation:
Assignee:
SJ S-Thomson Microelectronics SRL
International Classes:
G11C17/00; G11C7/00; G11C7/22; G11C16/02; G11C16/32; (IPC1-7): G11C7/00
Domestic Patent References:
| JP62284518A | ||||
| JP59151219A | ||||
| JP283885A |
Other References:
【文献】米国特許4687951(US,A)
【文献】欧州特許出願公開470719(EP,A1)
【文献】欧州特許出願公開470719(EP,A1)
Attorney, Agent or Firm:
Keiichi Yamamoto