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Patent Searching and Data


Title:
MASTER SLICE TYPE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPH0613587
Kind Code:
A
Abstract:

PURPOSE: To reduce the number of transistors employed and constitute a large- scale exclusive circuit for reading with a few number of transistors by a method wherein the number of bits, constituted by a reading exclusive memory circuit or 4-bit data pattern groups, which are constitutable, are selected and read out.

CONSTITUTION: A transistor 101, put on when a word line 108 is selected, supplies the potential of VDD to one diffusion area and connects the other diffusion area to the transistor row selecting wire 119 of N-channel transistor row, which constitutes the data of (0, 0, 0, 0). Another transistor 102, put on when another word line 109 is selected, supplies the potential of VSS to one diffusion area and connects the other diffusion area to the transistor row selecting wire 120 of a P-channel transistor row, which constitutes the data of (1, 0, 0, 0). By this method, necessary data can be read out with the number of transistors, which is fewer than the same so far.


Inventors:
OGUCHI YASUHIRO
Application Number:
JP16785292A
Publication Date:
January 21, 1994
Filing Date:
June 25, 1992
Export Citation:
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Assignee:
SEIKO EPSON CORP
International Classes:
G11C17/12; H01L21/82; H01L21/8238; H01L27/092; H01L27/10; H01L27/118; (IPC1-7): H01L27/118; G11C17/12; H01L27/092; H01L27/10
Attorney, Agent or Firm:
Kisaburo Suzuki (1 outside)