PURPOSE: To provide a phase control circuit which can simplify its control operation without controlling the reading phase of a memory even when an option circuit is added and also can omit the design restriction for the circuits of the precedent stages.

CONSTITUTION: The monitor circuits 17-19 monitor the input states of clocks and frame pulses received from the circuits 3-1-3-3 and 4-1-4-3 of the precedent stages and output these monitor results to a selection circuit 20. The circuit 20 selects one of those clocks and frame pulses based on the received monitor results and outputs it to a read counter 21. The counter 21 generates the read timings based on the clocks and frame pulses selected by the circuit 20 and outputs these timings to the memories 11-13 respectively. The memories 11-13 read the data received from those circuits of the precedent stages and written by the write timings given from the write counters 14-16 by the read timing given from the counter 21.