Title:
FREQUENCY CONVERSION CIRCUIT
Document Type and Number:
Japanese Patent JP3024534
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To make a video signal with a low frequency correspond to a liquid crystal display device corresponding to a dot clock frequency by allowing one system of a PLL circuit to generate a clock with a frequency division ratio corresponding to an RGB video signal and allowing the other system to generate a clock with a frequency division ratio calculated based on a horizontal synchronizing signal frequency and a frequency corresponding to the liquid crystal display device.
SOLUTION: A signal generated by write reset generators 13, 12 is given to a line memory 2, which writes digital RGB video data by a count generated from a frequency divider 14, by 540 clocks in this case. On the other hand, a CLK 52 generated by a VCO 20 is given to a frequency divider 25. The frequency divider 25 counts number of the clocks CLK 52 by 1588 counts and resets its counter at 1580-th count. Furthermore, the count is decoded and the frequency divider 25 provides a count-down clock output, the output and the horizontal synchronizing signal are given to a phase comparator 26, where the phases are compared and its error voltage is given to a PLL 21. The PLL 21 is configured to provide its output to the VCO 20. Thus, the phase relation between the horizontal synchronizing signal and the CLK 52 is maintained.
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Inventors:
Ken Morimoto
Application Number:
JP34251995A
Publication Date:
March 21, 2000
Filing Date:
December 28, 1995
Export Citation:
Assignee:
NEC
International Classes:
H04N5/66; H04N7/01; (IPC1-7): H04N7/01; H04N5/66
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)