Title:
CMLCMOS CONVERSION CIRCUIT
Document Type and Number:
Japanese Patent JP3003625
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To operate at a high speed by using first and second resistor as loads for first and second bipolar transistor constituting a differential circuit so as to generate latch up, etc., even when a power source voltage is low.
SOLUTION: The collector of a bipolar transistor Q101 constituting a differential circuit 10 is connected with a power source VDD through a resistor R101. On the other hand, the collector of a bipolar transistor Q102 is connected with the power source VDD through a resistor R102. Then the values of the resistors R101 and R102 are set so as to unconduct an N-channel MOS transistor M101 by voltage drop caused by the flowing of a current through the resistor R101 when the transistor Q101 is conducted. In addition, the values of the resistors R101 and R102 are set so as to unconduct an N-channel MOS transistor M102 by voltage drop caused by the flowing of a current through the resistor R102 when the transistor Q102 is conducted.
Inventors:
Osamu Nakauchi
Application Number:
JP14810497A
Publication Date:
January 31, 2000
Filing Date:
June 05, 1997
Export Citation:
Assignee:
NEC
International Classes:
H03K19/0175; H03K19/0948; (IPC1-7): H03K19/0175
Attorney, Agent or Firm:
Tadashi Wakabayashi