PURPOSE: To enable responding to the altering of a memory capacity while simplifying circuit in the perimeter of the memory by performing a write/read accessing of a word line of a memory cell array through a word line access circuit for writing and a word line access circuit for reading both arranged in a shift register structure.

CONSTITUTION: A data is inputted into a memory cell array 12 from an input buffer 21. An input clock corresponding to the input data is compared with a reference clock by means of a frequency comparison circuit 25 so that a writing clock corresponding to the resulting frequency difference is generated to be applied to a word line access circuit 22 for writing. In this manner, a word line WL is accessed sequentially to write the input data into a memory cell array 12. Then, the reference clock is applied to a word line access circuit 23 for reading and the word line WL is accessed sequentially to read out a data. This enables responding even to the altering of a memory capacity while simplifying circuits in the perimeter of a memory cell.