PURPOSE: To obtain a phase comparator circuit realizing a retiming of data without use of a delay circuit by providing a dissidence detection circuit detecting the dissidence between a phase of preceding/succeeding data and a phase of a clock when the clock is extracted from a data stream.

CONSTITUTION: A latch circuit 10 is made up of 8 D flip-flop circuits FF1-FF8 arranged in parallel. Data are received from a common input DIN by using clock signals CK0-CK7 whose phases differ by 45° as trigger signals and data DT0-DT7 are provided as outputs to a dissidence detection circuit 20 from a Q output. The circuit 20 employs exclusive NORs EXNOR1-EXNOR8 to compare data fetched by using odd number clock signals CK1, 3, 5, and data fetched by using even number (preceding and succeeding number to the odd number) clock signals CK2, 4, 6, 8. Retiming of the data is obtained by providing an output to an up-down signal generating circuit 30 depending whether the phases of the preceding/-succeeding clock signals are led to or lagged from the phase of the data.