Title:
SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JP2567180
Kind Code:
B2
Abstract:
PURPOSE: To utilize that a memory address is multiplexed, to end the operation of a programer circuit by using an address inputted previously, to immediately change the decoding state of a programable decoder receiving an output from the programer circuit and to output a signal showing whether a redundant memory cell is selected or not from the input of address whose order is later in a short time.
CONSTITUTION: Redundant memory cells RM are provided in divided plural memory cell arrays MCA0, MCA1, MCA2, MCA3 respectively, and a column decoder CD is shared. Four programer circuits PC0, PC1, PC2, PC3 to which a row address (X) is connected are provided. Further, the programable decoder PD to which a column address (Y) is connected whose decoding state is changed by program signals P0, P1, P2, P3 being the outputs of these programer circuits, and a redundant memory cell selection signal RSL showing whether the redundant memory cell is selected or not is outputted to a redundant memory cell selection line in the column decoder CD.
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Inventors:
NAMEGAWA TOSHIMASA
OKADA YOSHIO
OKADA YOSHIO
Application Number:
JP6497992A
Publication Date:
December 25, 1996
Filing Date:
March 23, 1992
Export Citation:
Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
G11C11/413; G11C11/401; G11C29/00; G11C29/04; H01L21/822; H01L27/04; H01L27/10; (IPC1-7): G11C29/00; G11C11/413
Domestic Patent References:
| JP6240700A |
Attorney, Agent or Firm:
Takehiko Suzue
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