Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH0613623
Kind Code:
A
Abstract:
PURPOSE: To attain a vertical type transistor logic and its circuit having a smaller surface area, improved short channel action, channel length variation, and a leakage current. CONSTITUTION: A transistor 10 has a substrate 12 and diffusion region 14. Gate conductive layers 18 have sidewalls formed by an aperture laid on the substrate 12 and allowed to expose the substrate 12. Sidewall dielectric layers 22, formed laterally adjacently to the sidewalls of the conductive layers 18, function as the gate electrodes of TRs. A conductive region formed in the aperture has a channel region 30 laterally adjacent to the layers 22 and 1st and 2nd current electrode regions 28, 34. When plural TRs 10 are laminated vertically, a logic gate of plural inputs such as an NMOS or PMOS NAND or NOR inverted gate and/or a CMOS NAND or NOR inverted gate is formed.
Inventors:
JIYON TEI FUITSUCHI
KARUROSU EI MAZUUA
KIISU II UITETSUKU
KARUROSU EI MAZUUA
KIISU II UITETSUKU
Application Number:
JP6309593A
Publication Date:
January 21, 1994
Filing Date:
February 26, 1993
Export Citation:
Assignee:
MOTOROLA INC
International Classes:
H01L27/00; H01L21/336; H01L21/822; H01L21/8238; H01L27/06; H01L27/088; H01L27/092; H01L29/78; H01L29/786; (IPC1-7): H01L29/784; H01L27/00; H01L27/092; H01L21/336
Attorney, Agent or Firm:
Yoshiaki Ikeuchi
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