PURPOSE: To make it possible to carefully control the asynchronous writing and reading of digital information by the storage state of a memory by providing the data processor with control means for performing prescribed operation when the writing access address to the memory and a reading out access address therefrom are equal.

CONSTITUTION: The writing/reading(W/R) controller 30 receives the writing and reading commands from the data processor and CRT terminals respectively in order to control the writing and reading of the memory 48. The W/R controller 30 sends the corresponding writing and reading signals to a multistage writing address ring counter 32 via a writing line 34 and to a multistage reading address ring counter 36 via a reading line 38. A comparator 40 is connected to both counters 32, 36. When both counters are equal, the memory is empty in case the last memory operation is the reading operation and the memory is full in case the last memory operation is the writing operation and, therefore, the next operations are respectively prohibited.