PURPOSE: To provide a pine-lined CPU in which an instruction with a variable length can be executed, and a memory using a variable data width is referred to.
CONSTITUTION: This multiprocessor includes a CPU 10 which is connected through a system bus 11 to a system memory 12 and an I/O element 13. When the CPU 10 fetches an instruction, a virtual instruction cache 17 is checked, and when a cache miss occurs, an address is converted into a physical address, and a primary cache 14 is checked. When the instruction is not present in the primary cache, access to a backup cache 15 is performed. The CPU 10 fetches a macro instruction from an instruction unit 22, decodes one by one in one cycle, resolves an operand designator, starts the fetching of an operand, and the operation is executed by an executing unit or an E box 23. A floating point processor 27 is an executing unit for a floating point and integer multiplying instruction, and the operand and a command are received, and the result is returned to the executing unit.
GIRUBAATO UORURITSUCHI
DEIBUITSUDO DEBUARERU
