PURPOSE: To make a recording circuit small in size by generating and storing a picture information compression data in each of a picture element direction and a line direction based on a 1-bit delay and a 2-bit delay digital picture signal.

CONSTITUTION: A digital picture data (a) by a line sensor camera is converted into a 1-bit delay digital picture data (b) and a 2-bit delay digital picture data (c) at shift registers 21, 22 of a picture element direction picture information recorder 20 respectively. The data a-c are processed by an arithmetic circuit 23 to obtain an arithmetic result X(=1a+2b-c) and the result is compared with two reference values at a level comparator circuit 24 to obtain a tri-state levels. The data is compressed in the direction of the picture element for each area represented by the tri-state levels and the compressed data is recorded in a picture element direction compressed picture information recording means 25 via required level addition circuits 25-27. Similarly, a line direction compression data is recorded in a line direction compression picture information recording circuit 38 of a line direction compression picture information recorder 30, the recording circuit is made small to enhance the recording efficiency.