Title:
HIGH SPEED VARIABLE LENGTH DECODER
Document Type and Number:
Japanese Patent JP3022784
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To apply variable length decoding at a high signal processing frequency to data subject to variable length decoding by conducting independently a generating operation of a 'run, level' symbol and a run level decoding operation.
SOLUTION: An interface section 12 reads variable length coding data from an FIFO memory 11 in response to a data request signal from a barrel shifter section 14. The barrel shifter section 14 provides an output of variable length coding data shifted by a code length according to a command of a code table 15 to a 'run, level' table 16 and provides an output of a 'run, level' symbol corresponding to a code word in the input data to an FIFO memory 37. The data are stored in a 'rvun, level' decoder 38 in the order of receipt and when the decoder is filled up, a fill signal is outputted to a sequence control section 33 to stop the operation of the interface section 12 and the barrel shifter section 14. High speed decoding is conducted by conducting independently the production of the 'run, level' symbol and the decoding in this way.
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Inventors:
Literary law
Application Number:
JP27496196A
Publication Date:
March 21, 2000
Filing Date:
October 17, 1996
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
H04N19/423; H03M7/42; H03M7/46; H04N1/41; H04N7/24; H04N19/00; H04N19/44; H04N19/625; H04N19/91; H04N19/93; (IPC1-7): H03M7/46; H04N1/41; H04N7/24
Domestic Patent References:
| JP61107818A | ||||
| JP63132530A | ||||
| JP63148789A |
Attorney, Agent or Firm:
Tadahiko Ito (1 outside)