PURPOSE: To attain a high speed operation, the low power consumption and the low radiation with a digital signal processing circuit by providing RAMs to store the data and the coefficients and connecting the multipliers to these RAMs.

CONSTITUTION: In regard of the input to a K register 31 of a multiplier 51, the outputs of the data RAM 11 and 12 are selected by a selector 91. In the same way, the outputs of the coefficient RAMs 21 and 22 are selected by a selector 93 in regard of the input to an L register 41. Meanwhile the outputs of the RAMs 11 and 12 are selected by a selector 92 in regard of the input to a K register 32 of a multiplier 52. In the same way, the outputs of the RAMs 21 and 22 are selected by a selector 94 in regard of the input to an L register 42 respectively. Then the outputs of both multipliers 51 and 52 are added together at the final stage and held in an M register 6 and then cumulatively added by an arithmetic circuit 7 and stored in an accumulator 8. Thus the multipliers 51 and 52 work in parallel to each other to share the operations with switching of the selectors 91-94. Therefore, the speed can be halved for the equivalent operation together with reduction of power consumption and occurrence of radiation.