PURPOSE: To increase the read speed by dividing many data lines in a memory array into plural subblocks and selectively connecting a sub-read line to a main read line by a second switch provided in each subblock.
CONSTITUTION: Sub-read line pairs SIO to SIOm and a main read line pair MIO are wired perpendiocular to data lines D1 to Dk and in parallel with a word line ML. First switches SS1 SSk which connect data lines and subread line pairs are divided into (m) subblocks, and only sub-read pair lines in one subblock out of them are connected to the main read in pair by second switches SB1 to SBm. When hey are divided into 16 subblocks and sub-read line pairs, 32 first switches and 16 second switches, in total, 48 switches are required to reduce the number of switches. Therefore, the load capacity is reduced, and the signal delay due to the load capacity of read line pairs is reduced, thereby performing the read operation at a high speed.
| JPH04195893 | SEMICONDUCTOR MEMORY DEVICE |
| JPS6034193 | [Title of the Invention] Static memory cell |
| JPH01185895 | SEMICONDUCTOR MEMORY |
KITSUKAWA GORO
KAWAJIRI YOSHIKI
KAWAHARA TAKAYUKI
KAWASE YASUSHI
KATO SHISEI
TACHIBANA RIICHI
HITACHI DEVICE ENG