Title:
【発明の名称】出力レベル測定装置
Document Type and Number:
Japanese Patent JP2551936
Kind Code:
B2
Abstract:
PURPOSE:To measure an output level by a DC instrument by stopping a clock when the output of a sample circuit varies and placing a sample circuit in a static state. CONSTITUTION:A clock signal from an oscillator 1 is inputted to the sample circuit 4 through a NAND circuit 2 and its output is inputted to a comparator 6. The comparator 6 constitutes a means which expands an ECL level to, for example, a TTL level, an EX-OR circuit 8 constitutes a means which causes level variation in a constant direction, and a flip-flop 14 constitutes a means which fixes the state. Further, the NAND circuit 2 constitutes a means which inhibited by the NAND circuit 2 which the output (e) of the flip-flop 14 and the sample circuit 4 enters the static state, so that the high level VOH or low level VOL is measured by the DC instrument.
Inventors:
TATEBAYASHI YOSHIFUMI
Application Number:
JP10982986A
Publication Date:
November 06, 1996
Filing Date:
May 13, 1986
Export Citation:
Assignee:
YAMAGATA NIPPON DENKI KK
International Classes:
G01R31/28; G01R31/319; G01R31/26; (IPC1-7): G01R31/319
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)