Title:
【発明の名称】半導体記憶装置
Document Type and Number:
Japanese Patent JP3071600
Kind Code:
B2
Abstract:
A semiconductor integrated circuit device produces an internal step-down power voltage (Vint) from an external voltage (Vext) for selectively distributing the internal step-down power voltage (Vint) and the external voltage (Vext) to the circuit components thereof, and a built-in step-down voltage generator (26) has two internal voltage generating circuits selectively enabled with a control signal (Sdc) for a standard data access mode and a burn-in test operation, wherein a premonitoring circuit (24) activates a current mirror circuit (25a) for producing the control signal (Sdc) when the external voltage (Vext) becomes close to an accelerating voltage range for the burn-in test operation, thereby decreasing standby current in the standard data access mode.
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Inventors:
Koji Koshikawa
Application Number:
JP6265893A
Publication Date:
July 31, 2000
Filing Date:
February 26, 1993
Export Citation:
Assignee:
NEC
International Classes:
G05F1/56; G05F1/46; G11C5/14; G11C11/401; G11C11/407; G11C29/00; G11C29/14; H02J1/00; (IPC1-7): G11C11/407; G05F1/56; H02J1/00
Domestic Patent References:
| JP2299034A | ||||
| JP6326900A | ||||
| JP3160699A |
Attorney, Agent or Firm:
Yusuke Omi