Title:
MANUFACTURE OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2561015
Kind Code:
B2
Abstract:
PURPOSE: To decrease the step of the surface of an interlayer insulating layer formed in the sharp shape at the upper part of the edge of a barrier metal pattern, which is patterned by anisotropic etching.
CONSTITUTION: A contact hole 8 is formed in an insulating film 7 on a semiconductor substrate 1, and barrier metal 20 is formed on the entire surface. With a mask pattern 25 as a mask, the barrier metal 20 undergoes anisotropic etching, and a barrier metal 10 is formed. Thereafter, with the same mask pattern 25 as a mask, a barrier metal pattern 30 is formed at a part where a peripheral corner part 21 of the barrier metal pattern 10 is etched out by isotropic etching. An interlayer insulating film 12 is formed on the entire surface. An opening part 13, wherein the upper surface of the barrier metal pattern 30 is exposed, is formed in the interlayer insulating film 12. A wiring layer 14, which is connected to the barrier metal pattern 30 through the opening part 13 and extending on the interlayer insulating film 12, is formed.
Inventors:
MATSUDA HIROO
Application Number:
JP31241693A
Publication Date:
December 04, 1996
Filing Date:
December 14, 1993
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L21/28; H01L21/768; H01L21/8242; H01L23/522; H01L27/10; H01L27/108; (IPC1-7): H01L21/768; H01L21/28; H01L21/8242; H01L27/108
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)