Title:
LOGIC CIRCUIT MINIMIZING DEVICE
Document Type and Number:
Japanese Patent JP2560990
Kind Code:
B2
Abstract:
PURPOSE: To provide minimizing capability and minimization with high accuracy by performing the minimization of a large scale logic circuit of multiple stages with small memory capacity and at high speed and furthermore, using a transition IF-THEN graph.
CONSTITUTION: A logic circuit of multiple stages is inputted to an input device 11, and the transition IF-THEN graph is generated by a transition IF-THEN graph generator 2. Furthermore, the transition IF-THEN graph is deformed by a transition IF-THEN graph deforming device 13. A partial circuit generator 14 generates a partial circuit than can be attached on the logic circuit inputted to the input device 11 from a deformed transition IF-THEN graph, and also, circuit redundancy generated by such attachment can be decided uniquely. An attaching partial circuit is added by a partial circuit attaching device 15, and the redundancy is eliminated by a redundancy eliminator, then, a minimization circuit can be obtained.
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Inventors:
YUGUCHI MASAYUKI
Application Number:
JP20486693A
Publication Date:
December 04, 1996
Filing Date:
August 19, 1993
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
G06F17/50; (IPC1-7): G06F17/50
Attorney, Agent or Firm:
Yoshiyuki Iwasa