PURPOSE: To obtain a large output current while suppressing the increase in a pattern area by selecting either of plural potential data and outputting the selected data via an output circuit.

CONSTITUTION: Selection data Da0,Db0 are inputted to a sample-and-hold circuit 11, held therein synchronously with a clock L and the inverse of L and resulting data Da1,Db1 are sent to a decoder 13. In the decoder 13, control signals 13a, the inverse of 13a, control signals 13b, the inverse of 13b, control signals 13c, the inverse of 13c, and control signals 13d, the inverse of 13d are generated in response to the combination of logic levels and they are sent to a multiplexer 15, in which one of analog switches 15a-15d is closed. Thus, Any of potential data Va-Vd is outputted to a node N3 as a signal 15Q via a switch to be turned on. The signal 15Q is inputted to an N-channel transistor(TR) 16b of a source follower amplifier 16. Then a signal Q having a same potential as the selected potential data is outputted from an output terminal node N4 of the amplifier 16.