Title:
【発明の名称】半導体装置の製造方法
Document Type and Number:
Japanese Patent JP3027864
Kind Code:
B2
Abstract:
A process for manufacturing a semiconductor device is described comprising the steps of providing window openings in a photoresist mask layer for forming trench grooves on the surface of a p+-type epitaxial silicon wafer where an integrated circuit is subsequently formed; providing window openings in the photoresist mask layer for forming dummy etched grooves in a scribe line zone on the wafer; and performing dry etching to remove material exposed by the window openings. The sum of the areas to be etched by dry etching accounts for not less than 5% of the total surface area on one side of the p+-type silicon wafer. Trench grooves are formed in the integrated circuit region of the wafer and dummy etched grooves are formed in a scribe line zone of the wafer. Both the trench grooves and the dummy etched grooves are filled with polycrystalline silicon to provide a smooth wafer surface. The wafer is then cleaved along the scribe line zone. Accordingly, a high density of circuit elements can be realized by forming microminiature etching sections in a stable configuration while preventing side etching during the dry etching processing step. The semiconductor device resulting from the disclosed process is also described.
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Inventors:
Atsuo Hirabayashi
Application Number:
JP6866491A
Publication Date:
April 04, 2000
Filing Date:
April 02, 1991
Export Citation:
Assignee:
Fuji Electric Co., Ltd.
International Classes:
H01L21/302; H01L21/301; H01L21/3065; H01L21/76; H01L21/78; H01L27/08; (IPC1-7): H01L21/3065; H01L21/76
Domestic Patent References:
| JP6289331A | ||||
| JP63211722A | ||||
| JP6317528A | ||||
| JP1313956A |
Attorney, Agent or Firm:
Masaharu Shinobe