PURPOSE: To provide the structure of a semiconductor memory wherein a memory cell area and bit line capacitance are reduced.

CONSTITUTION: A groove as part of a device isolation region is buried with an insulator 102, two conductors 103 on the side walls of the former, and an insulator 104 with which a remaining portion of the groove is buried. In this construction, the two conductors 103 serve as bit lines and are connected with a second bit line connected with a sense amplifier through a selection gate. A memory cell connected to the first bit line constitutes a sub array, and a plurality of the sub arrays are connected with a second bit line. Since the first bit line is buried in the device isolation region, the arrangement thereof is facilitated to reduce a memory cell area. The first bit line is made thinner and it is not needed to be lengthened, so that capacitance is reduced.