Title:
METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JP3046114
Kind Code:
B2
Abstract:
PURPOSE: To provide the flattered and multilayered semiconductor integrated circuit device capable of forming a resist in stably overhang shape as well as being easily manufactured by lifting-off step.
CONSTITUTION: The title manufacturing method of semiconductor integrated circuit device is composed of the four steps enumerated as follows i.e., the first step of forming a polyimide base resin layer 24 (27) on a Si substrate 21, the second step of forming positive type photoresist 25 on the polyimide base resin layer 24 to be processed so that the solubility of the polyimide base resin 24 to the same solvent solving the region sensitized by the resin 24 and the positive type photoresist 25 using the developing pattern of the photoresist 25 as a mask may exceed the solubility of the photoresist 25, the third step of etching away the photoresist 25 in overhang shape to form the first layer conductor metal 26 on the whole surface and the fourth step of removing the positive type photoresist 25 to form the second layer conductor metal 29.
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Inventors:
Kimiya Ichikawa
Hotta Hajime
Hotta Hajime
Application Number:
JP30016591A
Publication Date:
May 29, 2000
Filing Date:
November 15, 1991
Export Citation:
Assignee:
Oki Electric Industry Co., Ltd.
International Classes:
H01L21/28; H01L21/768; (IPC1-7): H01L21/768; H01L21/28
Domestic Patent References:
| JP4326722A |
Attorney, Agent or Firm:
Mamoru Shimizu (3 outside)