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Patent Searching and Data


Title:
SEMICONDUCTOR MEMORY AND READING METHOD THEREFOR
Document Type and Number:
Japanese Patent JPH0729383
Kind Code:
A
Abstract:

PURPOSE: To provide a reading circuit capable of expanding the reading room of a memory and reducing patterns and a peak current and a semiconductor storage device capable of operating a reading system using this circuit.

CONSTITUTION: A voltage variable circuit 9 for supplying a plurality of different sized potentials to word lines W1, W2,... is added to the semiconductor storage device for writing data of over 4 values in a memory cell 1. Then, by changing the size of a voltage impressed to the word line using this circuit, the data is read out. The reading operation is carried out being divided into plural times so as to read out the specified memory cell everytime the size of the voltage is changed. As the voltage used for the voltage variable circuit is the one equal to the threshold valve of the memory cell, the memory cell may be used, a power voltage is decreased and supplied.


Inventors:
SUGIURA NOBUTAKE
KATO HIDEO
MOCHIZUKI YOSHIO
Application Number:
JP19387693A
Publication Date:
January 31, 1995
Filing Date:
July 12, 1993
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
G11C11/56; G11C16/02; G11C16/04; G11C16/06; H01L21/8246; H01L27/112; (IPC1-7): G11C16/04; G11C11/56; H01L21/8246; H01L27/112
Attorney, Agent or Firm:
Toshi Takemura