Title:
SAMPLE-HOLD CIRCUIT
Document Type and Number:
Japanese Patent JP3033346
Kind Code:
B2
Abstract:
PURPOSE: To prevent the occurrence of a differential voltage between an input and an output due to a control switch in a sample-hold circuit.
CONSTITUTION: This circuit is constituted so that the differential voltage of a sample-hold circuit controlled by the same control signal and having at least two equal switches whose input signals are different each other is canceled by a subtracter. The differential voltage due to that a part of the control signal leaks to an output terminal side through the stray capacitance of a transistor constituting the switch is canceled. Thus, no differential voltage between an input voltage and an output voltage occurs, and the output voltage equal to the input voltage is held, and it is effective when a minute voltage easy to be affected by the differential voltage is inputted in particular. Further, even when the stray capacitance of the switch is fluctuated due to the influence of the fluctuation of source voltage and the dispersion, etc., of ambient temperature and a process, this circuit is hardly affected by these fluctuation.
Inventors:
Mihiro Nonoyama
Application Number:
JP17535592A
Publication Date:
April 17, 2000
Filing Date:
July 02, 1992
Export Citation:
Assignee:
Seiko Epson Corporation
International Classes:
G11C27/02; (IPC1-7): G11C27/02
Domestic Patent References:
| JP61129964A | ||||
| JP2146194A | ||||
| JP58121831A |
Attorney, Agent or Firm:
Kisaburo Suzuki (1 outside)
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