PURPOSE: To speed up data transfer by the common memory controller for the multiprocessor system with memory-size data bus width twice as wide as MPU-side data bus width without being limited to the MPU-side data bus width.
CONSTITUTION: This common memory controller is provided with memory data control parts 1a and 1b which output memory-side data (32-byte width) once at the time of the writing operation of MPUs 4a-4d each time MPU-side data (16-byte width) are inputted twice and output the MPU-side data twice in the reading operation each time the memory-side data are fetched once, an MPU-side selector 2 which connects the data buses of the MPUs 4a-4d, which are allowed to be accessed, to the MPU-side data bus 21a or 21b of the memory data control part 1a or 1b, and a memory-side selector 3 which select two 16-byte data of the memory data control parts 1a and 1b in order when the memory is accessed once and connects them to the memory data buses; and the memory data control parts 1a and 1b are controlled repeatedly in order irrelevantly to a memory cycle time to speed up the data transfer without being limited to the MPU-side data bus width.
KUBOTA KENJI
OTAKI MASAHIKO
ISHIMOTO SHIGENOBU
HARADA TOMOHIRO
KATAKURA YUJI
HITACHI VIDEO & INF SYST
HITACHI COMPUTER PERIPHERALS