Title:
【発明の名称】半導体集積回路
Document Type and Number:
Japanese Patent JP2601951
Kind Code:
B2
Abstract:
A semiconductor integrated circuit comprises a plurality of memory blocks each provided with a set of word lines shared by the other memory blocks so that the memory blocks may be accessed separately by using different address signals entered on a time division basis. The integrated circuit also comprises one or more than one decoders for choosing a word line from an end to allow access to any of the plurality of memory blocks and a word line latch circuit inserted into the set of word lines between a pair of memory blocks. With such an arrangement, the number of decoders, word lines, bit lines, memory cells and sense amplifiers as well as the overall size of the integrated circuit can be minimized. Besides, the access time to a certain memory block that constitutes a critical factor to determine the performance the entire integrated circuit can be curtailed so that it may be accessed in a very short period of time and consequently the performance of the circuit may be remarkably improved.
Inventors:
Kobayashi Tetsuo
Kazutaka Nogami
Kazutaka Nogami
Application Number:
JP198891A
Publication Date:
April 23, 1997
Filing Date:
January 11, 1991
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G11C11/401; G11C8/08; G11C11/00; G11C11/407; G11C11/413; (IPC1-7): G11C11/401; G11C11/407; G11C11/413
Domestic Patent References:
| JP2193394A | ||||
| JP63282996A | ||||
| JP2177192A |
Attorney, Agent or Firm:
Takehiko Suzue