Title:
SENSE AMPLIFIER DRIVING CIRCUIT
Document Type and Number:
Japanese Patent JP3185875
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To allow a high-speed sense amplification operation with a small layout area by comparing a reference voltage with a driving voltage that bas been fed back, by generating an output voltage according to the difference, by supplying the voltage to a gate with the output, and by responding to a control signal being supplied from the outside for short-circuiting the gate to the reference voltage.
SOLUTION: Each SAP circuit 11 is connected between a node G and reference potential GND, has an N-channel transistor Q2 where a control signal ΦS is inputted to the gate, and is connected between a differential amplifier 13 and the reference potential GND. When the potential of a word line WL0 rises to a specific level, information being written into a memory cell MC0 is outputted to a digit line DT0 at the side of the memory cell. When a high level is inputted to the memory cell, the potential of the digit line DT0 at the side of the memory rises slightly. A control line TG and a control signal ΦSAP1 are set to low and high levels, respectively, thus activating the SAP circuit 11.
Inventors:
Shuichi Tsukada
Application Number:
JP22818398A
Publication Date:
July 11, 2001
Filing Date:
August 12, 1998
Export Citation:
Assignee:
NEC
International Classes:
G11C11/409; G11C7/06; G11C11/401; G11C11/407; H01L21/8242; H01L27/108; (IPC1-7): G11C11/409; H01L21/8242; H01L27/108
Domestic Patent References:
| JP6162772A | ||||
| JP3222185A | ||||
| JP3290895A | ||||
| JP2172268A | ||||
| JP10125065A |
Attorney, Agent or Firm:
Yosuke Goto (1 person outside)