Title:
ネットリスト生成方法
Document Type and Number:
Japanese Patent JP7372117
Kind Code:
B2
Abstract:
To enable efficient search for a short-circuit danger location.SOLUTION: A second layout pattern with information of a plurality of nodes added is generated based on a first net list with nodes representing connections of a semiconductor integrated circuit and a first layout pattern representing wiring of the semiconductor integrated circuit. Separation distances between one or two or more sides of a first node and one or two or more vertices of a second node in the plurality of nodes are measured, respectively. When it is searched that the separation distances are smaller than or equal to the size of dust mixed in the semiconductor integrated circuit, it is determined that there is short-circuit danger locations between the first node and the second node, and short-circuit required location lists for making short-circuits between the first node and the second node with predetermined elements are generated. Each of the short-circuit required location lists is added to the first net list to generate a second net list for defect detection simulation.SELECTED DRAWING: Figure 6
Inventors:
Kazuhiko Arai
Application Number:
JP2019206605A
Publication Date:
October 31, 2023
Filing Date:
November 15, 2019
Export Citation:
Assignee:
Nisshinbo Microdevices Inc.
International Classes:
G06F30/33; G06F30/39; G06F30/398
Domestic Patent References:
| JP7121576A | ||||
| JP8055140A |
Foreign References:
| US20040153979 |
Attorney, Agent or Firm:
Sakai International Patent Office
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