Title:
NETWORK BUILDING
Document Type and Number:
Japanese Patent JPS63237175
Kind Code:
A
Abstract:
A provided logic circuitry implementation (Fig. 1) in a given technology includes n signals and m nodes. A final logic circuitry implementation (Fig. 3) is produced therefrom which is the functional equivalent of, and contains fewer connections than, the provided logic circuitry implementation. A selected one of the n signals is first processed (100), and global information is computed (200) for this signal. A graphical representation (Fig. 2) of connections between the m nodes is derived (300) from the computed global information. A list of nodes that form a cut-set is produced (400) from the graphical representation, and an optimized logic circuitry implementation is provided (500) as a function thereof. Each of the remaining ones of the n signals are processed sequentially (600), as above, to form successive optimized logic circuitry implementations, with the processing of the nth signal resulting in the final logic circuitry implementation.
Inventors:
CHIYAARUZU REONAADO BAAMAN
RUISU HEIN TOREBUIRIAN
RUISU HEIN TOREBUIRIAN
Application Number:
JP3299288A
Publication Date:
October 03, 1988
Filing Date:
February 17, 1988
Export Citation:
Assignee:
IBM
International Classes:
G06F17/50; (IPC1-7): G06F15/60
Attorney, Agent or Firm:
Hiroshi Kawabata (3 people outside)