Title:
三次元スタッキングを有するニューラルネットワークアクセラレータタイルアーキテクチャ
Document Type and Number:
Japanese Patent JP7058281
Kind Code:
B2
Abstract:
A three dimensional neural network accelerator that includes a first neural network accelerator tile that includes a first transmission coil, and a second neural network accelerator tile that includes a second transmission coil, wherein the first neural network accelerator tile is adjacent to and aligned vertically with the second neural network accelerator tile, and wherein the first transmission coil is configured to wirelessly communicate with the second transmission coil via inductive coupling.
Inventors:
Nowazik, Andreas Georg
Temamu, Olivier
Narayana Swami, Rabbi
Dasari, Udai Kumar
Temamu, Olivier
Narayana Swami, Rabbi
Dasari, Udai Kumar
Application Number:
JP2019552135A
Publication Date:
April 21, 2022
Filing Date:
May 11, 2018
Export Citation:
Assignee:
Google LLC
International Classes:
G06N3/063; H04B5/02
Domestic Patent References:
| JP201186738A |
Foreign References:
| WO2017057488A1 |
Other References:
Tadahiro Kuroda,"ThruChip Interface (TCI) for 3D Networks on Chip",Proceedings of 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip,2011年10月05日,Pages 238-241,ISBN: 978-1-4577-0170-2, .
Akio Nomura, et al.,"3D Shared Bus Architecture Using Inductive Coupling Interconnect",Proceedings of 2015 IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip,2015年09月25日,Pages 259-266,ISBN: 978-1-4799-8670-5,.
Yasuhiro Take, et al.,"3D NoC with Inductive-Coupling Links for Building-Block SiPs",IEEE TRANSACTIONS ON COMPUTERS,2012年10月12日,Vol.63, No.3,Pages 748-763,ISSN: 0018-9340,.
大久保徹以(外7名),「無線3次元積層チップを用いたDeep Learningアクセラレータのコンパイラツールチェーン」,電子情報通信学会技術研究報告,日本,一般社団法人 電子情報通信学会,2017年03月02日,Vol.116, No.510,第357~362頁,ISSN: 0913-5685.
Bilel Belhadj, et al.,"The Improbable But Highly Appropriate Marriage of 3D Stacking and Neuromorphic Accelerators",Proceedings of 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES),2014年10月17日,ISBN: 978-1-4503-3050-3,.
Akio Nomura, et al.,"3D Shared Bus Architecture Using Inductive Coupling Interconnect",Proceedings of 2015 IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip,2015年09月25日,Pages 259-266,ISBN: 978-1-4799-8670-5,
Yasuhiro Take, et al.,"3D NoC with Inductive-Coupling Links for Building-Block SiPs",IEEE TRANSACTIONS ON COMPUTERS,2012年10月12日,Vol.63, No.3,Pages 748-763,ISSN: 0018-9340,
大久保徹以(外7名),「無線3次元積層チップを用いたDeep Learningアクセラレータのコンパイラツールチェーン」,電子情報通信学会技術研究報告,日本,一般社団法人 電子情報通信学会,2017年03月02日,Vol.116, No.510,第357~362頁,ISSN: 0913-5685.
Bilel Belhadj, et al.,"The Improbable But Highly Appropriate Marriage of 3D Stacking and Neuromorphic Accelerators",Proceedings of 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES),2014年10月17日,ISBN: 978-1-4503-3050-3,
Attorney, Agent or Firm:
Fukami patent office
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