Title:
オフセット・スペーサ形成用の酸化に先立つ半導体基板への窒素のイオン注入方法
Document Type and Number:
Japanese Patent JP5220302
Kind Code:
B2
Abstract:
A method of formation of integrated circuit devices includes forming a gate electrode stack over a portion of a semiconductor. The stack includes a gate dielectric layer with a gate electrode thereabove. Implant diatomic nitrogen and/or nitrogen atoms into the substrate aside from the stack at a maximum energy less than or equal to 10 keV for diatomic nitrogen and at a maximum energy less than or equal to 5 keV for atomic nitrogen at a temperature less than or equal to 1000° C. for a time of less than or equal to 30 minutes. Then form silicon oxide offset spacers on sidewalls of the stack. Form source/drain extension regions in the substrate aside from the offset spacers. Form nitride sidewall spacers on outer surfaces of the offset spacers over another portion of the nitrogen implanted layer. Then form source/drain regions in the substrate aside from the sidewall spacers.
Inventors:
Cheejong Luo
Jin Hong Li
Thomas walter dia
Jin Hong Li
Thomas walter dia
Application Number:
JP2006310944A
Publication Date:
June 26, 2013
Filing Date:
November 17, 2006
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION
International Classes:
H01L21/336; H01L21/265; H01L21/8238; H01L27/092; H01L29/78
Domestic Patent References:
| JP2000269496A | ||||
| JP4206835A | ||||
| JP63261879A |
Attorney, Agent or Firm:
Takeshi Ueno
Tasaichi Tanae
Yoshihiro City
Hiroshi Sakaguchi
Tasaichi Tanae
Yoshihiro City
Hiroshi Sakaguchi
Previous Patent: JPS5220301
Next Patent: METHOD OF BRINGING COKE TO BE CHARGED INTO A BLAST FURNACE AND SIEVING THE SAME
Next Patent: METHOD OF BRINGING COKE TO BE CHARGED INTO A BLAST FURNACE AND SIEVING THE SAME