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Title:
NOISE ELIMINATING CIRCUIT
Document Type and Number:
Japanese Patent JPS64813
Kind Code:
A
Abstract:

PURPOSE: To easily make a circuit into a high density integrated circuit by providing a D-FF with a clear terminal and inputting an AND signal to the clock terminal and inputting a OR signal to the clear terminal.

CONSTITUTION: An input signal S10 has the waveform shaped by a Schmitt trigger circuit 1 and is inputted to a shift register 20 as a signal S12. The register 20 has a functional constitution to obtain four-stage shift outputs of the input signal and outputs signals S13∼S16. Signals S13∼S16 are processed in a four-input AND gate 30 by AND operation and are processed in a four-input OR gate 40 by OR operation. Processing outputs S18 and S17 are given to terminals CK and CLR of a D-FF circuit 5 with clear respectively, and the output where noise is eliminated is obtained from the output of the circuit 5. Thus, the circuit having the noise eliminating characteristic is constituted of a digital integrated circuit and the circuit is easily made into a high density integrated circuit.


Inventors:
ASADA HIROSHI
Application Number:
JP15609387A
Publication Date:
January 05, 1989
Filing Date:
June 23, 1987
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
H03K5/1252; C08L23/12; H03K5/01; (IPC1-7): H03K5/01
Domestic Patent References:
JPS52137964A1977-11-17
Attorney, Agent or Firm:
Takahisa Kimura



 
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