Title:
NOISE MARGIN INPUT CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPH05315938
Kind Code:
A
Abstract:
PURPOSE: To provide a noise margin input circuit device capable of individually setting up a noise margin and inverted potential to respective optimum values, setting up a large noise margin and holding the inverted potential at a TTL level.
CONSTITUTION: The noise margin input circuit device connected to the input side of an integrated circuit provided with plural n-channel MOS transistors(TRs) 1 to 4 is provided with an enhancement type n-channel MOS TR 5 connecting its drain to a positive power supply and adopting its gate as an input terminal, a load means 6 connecting one terminal to the source of an n-channel MOS TR and the input of the succeeding inverter and grounding the other terminal.
Inventors:
MIYANISHI EIJI
Application Number:
JP11880092A
Publication Date:
November 26, 1993
Filing Date:
May 12, 1992
Export Citation:
Assignee:
RICOH KK
International Classes:
H03K19/0185; H03K19/003; (IPC1-7): H03K19/0185; H03K19/003
Attorney, Agent or Firm:
Aoyama Ryo (2 outside people)