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Title:
NOISE REDUCTION CIRCUIT
Document Type and Number:
Japanese Patent JPH05219517
Kind Code:
A
Abstract:

PURPOSE: To allow one circuit to eliminate the noise of both a luminance and a chrominance signal by filtering a high frequency component from the noise component of a multiplex signal and subtracting the high frequency component from the input luminance signal and the input chrominance signal.

CONSTITUTION: A 2nd subtractor 55 subtracts the output noise component of a coefficient device 54 from the multiplex signal from an adder 51 and sends the result to a signal delay memory 52. On the other hand, a 2nd HPF 33 separates a high frequency component from a noise component of the output of a coefficient device 54 and adds the component to a 3rd subtractor 34 and the high frequency noise component is subtracted from the luminance signal at a luminance signal input terminal 31. Thus, the residual signal is outputted from a luminance signal output terminal 35. Furthermore, a 2nd LPF 44 separates a low frequency component from a noise signal outputted from the coefficient device 54 and adds the component to a 4th subtractor 45, the low frequency noise component is subtracted from the input chrominance signal via a 1st phase shifting device 42 to obtain the chrominance signal after noises are eliminated. Thus, one circuit is enough to eliminate the noises of both the luminance signal and the chrominance signal.


Inventors:
KOGA TAKASHI
KURIHARA KOICHI
Application Number:
JP9872091A
Publication Date:
August 27, 1993
Filing Date:
April 30, 1991
Export Citation:
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Assignee:
TOSHIBA CORP
TOSHIBA AVE KK
International Classes:
H04N5/21; H04N5/93; H04N5/937; H04N9/64; H04N9/77; H04N9/87; (IPC1-7): H04N5/21; H04N5/93; H04N9/64; H04N9/77; H04N9/87
Attorney, Agent or Firm:
Saichi Suyama (1 person outside)



 
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