PURPOSE: To reduce a circuit scale by obtaining the control signal of an alternative circuit selecting the output of a full adder circuit and '0' level from a gate circuit receiving a carry signal of the fill adder circuit of the most significant bit and a code bit of an original signal.

CONSTITUTION: The code bit A3 of the original signal A and a carry signal of the full adder circuit 6 are inputted to an exclusive OR circuit 5, from which the control signal 20 of the alternate circuits 10-13 selecting the output of full adder circuits 6-9 and '0' level is obtained. Thus, an absolute value circuit and a comparator used to generate the control signal for the alternative circuits are not required and the circuit scale of a noise reduction device is considerably reduced.