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Title:
ノイズ対策回路
Document Type and Number:
Japanese Patent JP7439490
Kind Code:
B2
Abstract:
To provide a noise countermeasure circuit capable of suppressing the transmission of external noise to the board ground while suppressing the number of noise countermeasure components.SOLUTION: A noise countermeasure circuit includes: a board provided with a plurality of signal sources and the board ground; a first shielded wire having a first signal line connected to the signal source and a first shield covering around the first signal line; a second shielded wire having a second signal line connected to the signal source and a second shield covering around the second signal line; and a common mode choke coil having a first coil and a second coil, the common mode choke coil being provided to the board. One end of the first coil is electrically connected to the first shield, the other end of the first coil is electrically connected to the board ground, one end of the second coil is electrically connected to the second shield, and the other end of the second coil is electrically connected to the board ground.SELECTED DRAWING: Figure 1

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Inventors:
Yasushi Saito
Yoshihiro Imanishi
Taro Higuchi
Yoshida Minehito
Miyuki Nojiri
Sayaka Sekiguchi
Hiroyuki Honda
Hiroo Igarashi
Application Number:
JP2019226612A
Publication Date:
February 28, 2024
Filing Date:
December 16, 2019
Export Citation:
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Assignee:
MURATA MANUFACTURING CO.,LTD.
International Classes:
H03H7/09; H01F27/00
Domestic Patent References:
JP2005318539A
JP2006080215A
JP2011244418A
JP2017022515A
Foreign References:
WO2009110354A1
WO2018168282A1
Attorney, Agent or Firm:
Sakai International Patent Office



 
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