Title:
スピンMOSトランジスタを用いた不揮発性メモリ回路
Document Type and Number:
Japanese Patent JP5023167
Kind Code:
B2
Abstract:
Certain embodiments provide a nonvolatile memory circuit in which a first p-channel MOS transistor and a first n-channel spin MOS transistor are connected in series, a second p-channel MOS transistor and a second n-channel spin MOS transistor are connected in series, gates of the first p-channel MOS transistor and the first n-channel spin MOS transistor are connected, gates of the second p-channel MOS transistor and the second n-channel spin MOS transistor are connected, a first n-channel transistor includes a drain connected to a drain of the first p-channel transistor and the gate of the second p-channel transistor, a second n-channel transistor includes a drain connected to a drain of the second p-channel transistor and the gate of the first p-channel transistor, and gates of the first and second n-channel transistors are connected.
Inventors:
Sugiyama Hideyuki
Satoshi Tanamoto
Marugame Takao
Mizukawa Megumi
Tomoaki Iguchi
Yoshiaki Saito
Satoshi Tanamoto
Marugame Takao
Mizukawa Megumi
Tomoaki Iguchi
Yoshiaki Saito
Application Number:
JP2010025821A
Publication Date:
September 12, 2012
Filing Date:
February 08, 2010
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G11C11/15; H01L21/8244; H01L21/8246; H01L27/10; H01L27/105; H01L27/11; H01L29/82; H01L43/08
Domestic Patent References:
| JP2009171007A |
Foreign References:
| WO2003105156A1 |
Other References:
Shuu'ichirou YAMAMOTO, Satoshi SUGAHARA,Nonvolatile Static Random Access Memory Using Magnetic Tunnel Junctions with Current-Induced Magnetization Switching Architecture,Japanese Journal of Applied Physics,日本,Japan Soceity of Applied Physics,2009年 4月20日,Vol.48,043001
Attorney, Agent or Firm:
Hirohito Katsunuma
Yasukazu Sato
Hiroshi Yoshimoto
Yasushi Kawasaki
Yasukazu Sato
Hiroshi Yoshimoto
Yasushi Kawasaki