To specify a write-in defective bit line.
This memory has a non-volatile memory cell array, an address buffer storing an address externally inputted, a decoder selecting plural non- volatile memory cells from the memory cell array in accordance with an address stored in the address buffer, a data register to which data from the plural non-volatile memory cells selected by the decoder is inputted and outputting these inputted data, plural external control signal input terminals, and data input/output terminals connected to the data register and the address buffer, a command input mode decided in accordance with combination of plural external control signals is permitted, when a register read-command is inputted to the input/output terminal in this command input mode, contents of the address buffer are outputted to the input/output terminal.
KATO HIDEO
ASANO MASAMICHI
TOKUSHIGE KAORU
YAMAMURA TOSHIO
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