Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND ITS MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JP2010080497
Kind Code:
A
Abstract:

To provide a device for suppressing advance of silicide formation of a lower electrode part in a selection gate transistor at the time of forming a silicide film of a control gate electrode film in a post-process and to provide a manufacturing method of the device.

In a NAND flash memory device, a gate electrode MG of a memory cell transistor is obtained by laminating a floating gate electrode part 51, an inter-electrode insulating film 6 and a control gate electrode part 71 through a gate insulating film 4 on a silicon substrate 1. The control gate electrode part 71 is silicided after a polycrystalline silicon film is formed. A gate electrode SG of the selection gate transistor is obtained by sequentially laminating a lower electrode part 5, an inter-electrode insulating film 6, an intermediate electrode part 7, an inter-electrode insulating film 8 and an upper electrode part 9. Since silicide reaction advances in the intermediate electrode part 7 and the lower electrode part 5 through opening parts 6a and 8a at the time of siliciding the upper electrode part 9 formed of the polycrystalline silicon film, advance of silicide reaction can be stopped before it reaches the gate insulating film 4.


Inventors:
KAI NAOKI
Application Number:
JP2008244106A
Publication Date:
April 08, 2010
Filing Date:
September 24, 2008
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
TOSHIBA CORP
International Classes:
H01L21/8247; H01L27/10; H01L27/115; H01L29/788; H01L29/792
Attorney, Agent or Firm:
Patent Business Corporation Sato International Patent Office