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Title:
プログラム動作を選択する不揮発性半導体メモリ装置
Document Type and Number:
Japanese Patent JP4068247
Kind Code:
B2
Abstract:
The disclosure is a nonvolatile memory device operable in a plurality of programming cycles, including, a memory cell array formed of a plurality of memory cells connected to bit lines and word lines, a plurality of data buffers for receiving a plurality of data bits, a plurality of write drive circuits disposed between the memory cell array and the data buffers, and a circuit for generating a plurality of selection signals for controlling the write drive circuits, in response to a current level of a power supply voltage. The selection signals determines the number of data bits programmed in one of the programming cycles.

Inventors:
Chung Hakusawa
Park Bell
Application Number:
JP37151998A
Publication Date:
March 26, 2008
Filing Date:
December 25, 1998
Export Citation:
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Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
G11C16/02; G11C16/06; G11C16/10; G11C16/30; H01L21/8247; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
JP5012891A
JP1125800A
JP6084396A
Attorney, Agent or Firm:
Masatake Shiga
Takashi Watanabe