Title:
NON-VOLATILE SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JP3560401
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To suppress the short channel effect by specifying the ratio of the capacitance between a drain region and a floating gate to the sum of the capacitance between a source region, a drain region and a control gate, a floating gate to be a value not exceeding a specific value.
SOLUTION: W1 and W2 respectively represent the gate width of the overlapped part among the source-drain region, a floating gate 4 and a control gate 6, and that of the overlapped part of the floating gate 4 and the control gate 6. Besides, L and Lov respectively represent the gate length and the overlapped length of the floating gate 4 and a drain region 8. Assuming the overlapping length Lov to be 0.132-0.191 when the first gate oxide film thickness Tox1 to be 32nm, the second gate oxide thickness Tox2 to be 26.5nm, the gate length 11 to be 1.1nm the first gate width W1 to be 1.0nm the second gate width W2 to be 3.0nm, CFD/CTOTAL can be set up exceeding 0.026 but not exceeding 0.038.
Inventors:
Tsuyoshi Kuzuhara
Noriyuki Iwamori
Noriyuki Iwamori
Application Number:
JP34104995A
Publication Date:
September 02, 2004
Filing Date:
December 27, 1995
Export Citation:
Assignee:
株式会社デンソー
International Classes:
H01L21/8247; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): H01L21/8247; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
| JP5630769A | ||||
| JP577162A |
Attorney, Agent or Firm:
Hirohiko Usui
Kazuyuki Yahagi
Kazuyuki Yahagi
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