Title:
不揮発性半導体記憶装置
Document Type and Number:
Japanese Patent JP4133166
Kind Code:
B2
Abstract:
An electrically programmable and erasable non-volatile semiconductor memory such as a flash memory is designed into a configuration in which, when a cutoff of the power supply occurs in the course of a write or erase operation carried out on a memory cell employed in the non-volatile semiconductor memory, the operation currently being executed is discontinued and a write-back operation is carried out to change a threshold voltage of the memory cell in the reversed direction. In addition, the configuration also allows the number of charge-pump stages in an internal power-supply configuration to be changed in accordance with the level of a power-supply voltage so as to make the write-back operation correctly executable. As a result, no memory cells are put in deplete state even in the event of a power-supply cutoff in the course of a write or erase operation.
Inventors:
Sakurai Ryotaro
Hitoshi Tanaka
Toshifumi Noda
Koji Shigematsu
Hitoshi Tanaka
Toshifumi Noda
Koji Shigematsu
Application Number:
JP2002278905A
Publication Date:
August 13, 2008
Filing Date:
September 25, 2002
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
G11C16/02; G11C7/00; G11C11/34; G11C16/00; G11C16/06; G11C16/22; G11C16/30; G11C16/34; G11C11/56
Domestic Patent References:
| JP11501761A | ||||
| JP2000512054A | ||||
| JP2004014086A |
Attorney, Agent or Firm:
Shizuyo Tamamura