Title:
NONVOLATILE MEMORY CIRCUIT HAVING AUTOMATIC ERASING FUNCTION
Document Type and Number:
Japanese Patent JP3970070
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To prevent occurrence of an erasure error caused by that a sector of non-existence is selected and erasure operation is performed when a memory region has capacity being different from power of 2.
SOLUTION: A non-volatile memory circuit has a memory region having sectors of N pieces (N: the plural number) being different from power of 2, a sector selecting circuit decoding a sector address and selecting a sector corresponding to the sector address, and a memory control circuit changing successively the sector addresses and selecting the next sector when erasure operation is executed for a selected sector responding to an erasure command and finish of the erasure is verified, the memory control circuit selects the next sector without performing erasure operation for the sector when a non-existence sector is selected in a memory region. As the memory control circuit selects the next sector without performing erasure operation for the sector when a non-existence sector is selected in a memory region, it can be prevented that the non-existence sector is selected, finish of erasure is not verified, and an erasure error is caused.
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Inventors:
Junya Kawamata
Application Number:
JP2002078796A
Publication Date:
September 05, 2007
Filing Date:
March 20, 2002
Export Citation:
Assignee:
富士通株式会社
International Classes:
G11C16/02; G11C16/16; G11C16/22; (IPC1-7): G11C16/02
Domestic Patent References:
| JP2001195892A | ||||
| JP10241377A | ||||
| JP2000260183A |
Attorney, Agent or Firm:
Kenji Doi
Hayashi Tsunetoku
Hayashi Tsunetoku